The present invention relates to synchronization detecting circuits which detect synchronization between receiving data and reference data in receiver units, provided in transmission systems, so as to test performance of data transmission.
Pseudo-random patterns (simply called `PN patterns`, where `PN` is an abbreviation for `Pseudo Noise`) are frequently used to test performance of communication devices, transmission devices, transmission lines and the like. There is provided a testing device which transmits or receives PN patterns to perform tests on the above devices. The testing device contains a receiver unit which detects synchronization between receiving data and reference data so that evaluation of the receiving data is performed. The receiver unit contains a pseudo-random pattern creating circuit (simply called a `PN creating circuit`) which creates reference PN patterns. A synchronization detecting circuit is provided to detect synchronization between the reference PN patterns and PN patterns received by the receiver unit.
FIG. 2 is a block diagram showing an example of a synchronization detecting circuit. The synchronization detecting circuit comprises a comparison circuit 11, a pattern comparison circuit 12, a coincidence detecting circuit 13 and a PN creating circuit 4. In addition, there are provided a receiving-data input 6, a detected-pattern input 17 and a synchronization-detection output 8. Herein, the receiving-data input 6 indicates input of receiving data, containing PN patterns, which are received by a receiver unit of a testing device through transmission lines or the like which are objects to be tested; and the detected-pattern input 17 indicates a certain part of the PN patterns included in the receiving data. The PN-pattern creating circuit 4 creates a reference PN pattern. The comparison circuit 11 compares the receiving-data input 6 with the detected-pattern input 17 so as to detect coincidence of data between them. When the coincidence of data Is detected, the comparison circuit 11 produces a detection pulse. The pattern comparison circuit 12 compares the detected-pattern input 17 with the reference PN pattern outputted from the PN-pattern creating circuit 4 so as to detect coincidence of data between them. When the coincidence of data is detected, the pattern comparison circuit 12 produces a detection pulse.
The coincidence detecting circuit 13 performs monitoring as to whether or not the comparison circuit 11 produces the detection pulse at a timing when the detection pulse of the pattern comparison circuit 12 occurs. If so, the coincidence detecting circuit 13 produces a synchronous detection signal at the synchronization-detection output 8. If not, the coincidence detecting circuit 13 produces an asynchronous detection signal.
Now, method in detection of synchronization will be explained. In general, the PN pattern has a property that if a number of PN stages is represented by `n` (where `n` is an integer), a pattern of n bits or more occurs only once consecutively in one period, i.e., In (2.sup.n -1) bits. For this reason, when detecting synchronization between receiving data and reference data, created by the PN creating circuit within the receiver unit, monitoring is performed as to whether or not the pattern of n bits occurs periodically at a timing at which both of the receiving data and reference data exist.
In FIG. 2, If a number of PN stages applied to the receiving-data input 6 is represented by `N` (where `N` is an integer), the detected-pattern input 17 corresponds to fixed patterns of N bits or more which are consecutively arranged in the PN pattern. As described before, the comparison circuit 11 produces a detection pulse when detecting coincidence between the receiving-data input 6 and the detected-pattern input 17, while the pattern comparison circuit 12 produces a detection pulse when detecting coincidence between the reference PN pattern, outputted from the PN pattern creating circuit 4, and the detected-pattern input 17.
An example of a comparison circuit is shown in FIG. 3. In FIG. 3, there are provided a PN-pattern input 31, a detected-PN-pattern input 32, a detection-signal output 33, D flip-flop circuits (DFF circuits) 34-1 to 34-N, exclusive-NOR circuits 35-1 to 35-N, an AND circuit 36 and a clock input 37. Herein, each of the DFF circuits is represented by a numeral `34`, while each of the exclusive-NOR circuits is represented by a numeral `35`.
The PN-pattern input 31 is delayed by the DFF circuit 34. The exclusive-NOR circuit 35 performs comparison between the PN pattern delayed and the detected-PN-pattern input 32 by each bit. If two inputs to the exclusive-NOR circuit 35 are the same, an output of the exclusive-NOR circuit 35 is `HIGH`. If the two inputs are different from each other, an output of the exclusive-NOR circuit 35 is `LOW`.
The AND circuit 36 yields a logical product between outputs of the exclusive-NOR circuits 35-1 to 35-N, so the AND circuit 36 receives `N` inputs. If all of the `N` inputs are `HIGH`, an output of the AND circuit 36 is `HIGH`. If not, an output of the AND circuit 36 is `LOW`. In short, only when all bits of the PN pattern delayed perfectly coincide with all bits of the detected-PN-pattern input 32, the detection-signal output 33 becomes `HIGH`.
When the receiving data, received by the receiver unit, are applied to the PN-pattern input 31, the comparison circuit of FIG. 3 serves as the comparison circuit 11 in FIG. 2. Similarly, when the output of the PN-pattern creating circuit 4 is applied to the PN-pattern input 31, the comparison circuit of FIG. 3 serves as the pattern comparison circuit 12 in FIG. 2. Herein, the detected-pattern input 17 is applied to the detected-PN-pattern input 32 of the comparison circuit of FIG. 3.
If the receiving data, received by the receiver unit, indicate a correct PN pattern which does not contain an error, and if synchronization exists between the receiving data and output of the PN creating circuit 4, both of the comparison circuits 11 and 12 periodically produce detection pulses at same timings.
There is a possibility that an error (or errors) occurs in the receiving-data input 6. In such an error event, there comes a moment at which the pattern comparison circuit 12 produces a detection pulse while the comparison circuit 11 does not produce a detection pulse. In order to cope with the error event, the coincidence detecting circuit 13 is provided to monitor as to whether or not the comparison circuit 11 produces a detection pulse when the pattern comparison circuit 12 produces a detection pulse. If coincidence of the detection pulses is detected, a synchronous detection signal is produced. If it is not detected, an asynchronous detection signal is produced.
The synchronization detecting circuit of FIG. 2 suffers from a problem that detection of synchronization cannot be performed unless all bits of the detected pattern in the receiving data are received correctly. This circuit suffers from another problem that detection of synchronization cannot be performed when transmitting and receiving testing data which are masked using a period irrelevant to the period of the PN pattern.
An example of the testing data, which are masked using the period irrelevant to the period of the PN pattern, are shown by FIG. 4A in connection with FIG. 4B. Each of numerals 41-1 and 41-2 represents an interval for consecutive `a` bits of a PN pattern, while each of numerals 42-1 and 42-2 represents a fixed interval for consecutive `b` bits which are `HIGH` or `LOW`. Incidentally, last data `D.sub.x ` of the interval 41-1 is followed by first data `D.sub.x+b ` of the interval 41-2.
The testing data of FIG. 4A have a period, represented by `a+b`, which is irrelevant to the period of the PN pattern. In such a period of the testing data, `b` bits are consecutively set at `HIGH` or `LOW`. So, when using data, which are masked responsive to a certain period irrelevant to the period of the PN pattern, as the testing data, there is a possibility that a detected pattern should be partially masked. In such a masked event, the synchronization detecting circuit of FIG. 2 cannot perform detection of synchronization well.